Datasheet

Clocks and Reset Generator (CRG)
Register Descriptions
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
ACQ — Acquisition
Write anytime. If AUTO =1 this bit has no effect.
0 = Low bandwidth software selected
1 = High bandwidth software selected
SCME — Self-clock mode enable
User mode: Write once
Test mode: Write anytime
0 = Detection of crystal clock failure causes crystal monitor reset
1 = Detection of crystal clock failure forces the MCU in self-clock
mode.
CRG RTI Control
Register (RTICTL)
This register initializes the RTI frequency.
Read and write anytime.
A write to this register will initialize the RTI counter.
RTR[6:4] — Real Time Interrupt Prescale Rate Select
These bits select the prescale rate for the RTI. See Table 47.
RTR[3:0] — Real Time Interrupt Modulus Counter Select
These bits select the modulus counter target value to provide
additional granularity. See Table 47.
Table 47 shows all possible divide values selectable by the RTICTL
register. The source clock for the RTI is OSCCLK.
Address Offset: $0007
Bit 7 6543210
Read: 0
RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
Write:
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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