Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
CRG PLL Control
Register (PLLCTL)
A description of the PLLCTL register follows:
Read anytime. Refer to each bit for write conditions.
CME — Crystal Monitor Enable
Write anytime.
0 = Crystal monitor is disabled.
1 = Crystal monitor is enabled. Slow or stopped clocks (including
the stop instruction) will cause a crystal failure reset sequence
or self-clock mode.
PLLON — Phase Lock Loop On
Write anytime except when PLLSEL = 1. In self-clock mode, the
output of the PLLON bit is forced to 1, but the PLLON bit reads the
latched value.
0 = PLL is turned off.
1 = PLL is turned on. If AUTO bit is set, the PLL will lock
automatically.
AUTO — Automatic Bandwidth Control
Automatic bandwidth control selects either the high bandwidth
(acquisition) mode or the low bandwidth (tracking) mode depending
on how close to the desired frequency the VCO is running.
Write anytime except when PLLWAI is set and AUTO bit is forced to 1.
0 = Automatic Mode Control is disabled and the PLL is under
software control, using ACQ bit.
1 = Automatic Mode Control is enabled and ACQ bit has no effect.
Address Offset: $0006
Bit 7 6543210
Read:
CME PLLON AUTO ACQ
000
SCME
Write:
Reset: 11110001
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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