Datasheet

Clocks and Reset Generator (CRG)
Register Descriptions
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
PLLWAI — PLL stops in WAIT mode
User mode: Write once
Test mode: Write anytime
If PLLWAI is set, PLLON and PLLSEL bits remain set during wait
mode but the PLL is powered down. Upon exiting wait mode, an
automatic recovery delay is imposed until LOCK is detected. AUTO
bit is forced to 1 if PLLWAI is set.
0 = Allows the PLL to keep running in wait mode.
1 = Disables the PLL whenever the part goes into wait mode.
CWAI — CLK24 and CLK23 stop in WAIT mode
User mode: Write once
Test mode: Write anytime
0 = Allows CLK24 and CLK23 to continue running in wait mode.
1 = Disables CLK24 and CLK23 whenever the part goes into wait
mode.
RTIWAI — RTI stops in WAIT mode
User mode: Write once
Test mode: Write anytime
0 = Allows the RTI to continue running in wait mode.
1 = Disables and initializes the RTI dividers whenever the part goes
into wait mode.
COPWAI — COP stops in WAIT mode
User mode: Write once
Test mode: Write anytime
0 = Allows the COP to continue running in wait mode.
1 = Disables and initializes the COP dividers whenever the part
goes into wait mode.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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