Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
PLLSEL — PLL selected for system clock
Write anytime except when LOCK is cleared and AUTO is set, or
TRACK is cleared and AUTO is cleared. In self-clock mode, the
output of the PLLSEL bit is forced to 1, but the PLLSEL bit reads the
latched value.
0 = SYSCLK is derived from OSCCLK.
1 = SYSCLK is derived from PLLCLK.
PSTP — Pseudo Stop
User mode: Write once
Test mode: Write anytime
In Pseudo-STOP mode, the oscillator is still running while the MCU is
maintained in STOP mode.
0 = Pseudo-STOP oscillator mode is disabled.
1 = Pseudo-STOP oscillator mode is enabled.
NOTE: Pseudo-STOP allows for faster STOP recovery and reduces the
mechanical stress and aging of the resonator in case of frequent STOP
conditions at the expense of a slightly increased power consumption.
SYSWAI — System clocks stop in WAIT mode
User mode: Write once
Test mode: Write anytime
0 = Allows the system clocks to continue running in wait mode.
1 = Disables all the system clocks (CLK24, CLK23, CLK3 and
OSCCLK) whenever the part goes into wait mode.
NOTE: RTI and COP are not affected by SYSWAI bit.
ROAWAI — Reduced Oscillator Amplitude in WAIT mode
User mode: Write once
Test mode: Write anytime
0 = Normal peak-peak oscillator amplitude in wait mode.
1 = Reduced peak-peak oscillator amplitude in wait mode.
NOTE: Lower peak to peak oscillator amplitude exhibit lower power
consumption but could have adverse effects during any
Electro-Magnetic Susceptibility (EMS) tests.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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