Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
1 = Set when a power on reset has occurred
LOCKIF — PLL Lock Interrupt Flag
This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 = No change in LOCK bit
1 = LOCK condition has changed, either from a locked state to an
unlocked state or vice versa.
LOCK — Lock Status
Write never. This bit is cleared in Self-Clocked Mode as the lock
detector can not operate without the reference frequency.
0 = PLL VCO is not within the desired tolerance of the target
frequency.
1 = After the PLL is turned on, indicates the PLL VCO is within the
desired tolerance of the target frequency.
TRACK — Track Status
Write never. This bit is cleared in Self-Clocked Mode as the lock
detector can not operate without the reference frequency. See
Acquisition and tracking Modes for more information.
0 = Acquisition mode status.
1 = Tracking mode status.
SCMIF — Self-clock mode Interrupt Flag
The flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 = No change in SCM bit.
1 = SCM condition has changed, either entered or exited self-clock
mode.
SCM — Self-clock mode Status
Write never. See Crystal loss, stop and startup for more information.
0 = MCU is operating normally with OSCCLK available.
1 = PLL self-clock is supplied to the MCU upon loss of OSCCLK.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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