Datasheet

Clocks and Reset Generator (CRG)
Register Descriptions
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
CRG Test Flags
Register (CTFLG)
The CTFLG register is reserved for test mode only.:
Read: always read $00 except in test modes.
Write: only in test modes.
CRG Flags Register
(CRGFLG)
Read anytime. Refer to each bit for write conditions.
RTIF — Real Time Interrupt Flag
The RTIF bit is automatically set to one at the end of every RTI period.
This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 = Time-out has not yet occurred.
1 = Set when the time-out period is met.
PORF — Power on Reset Flag
The PORF bit is automatically set to one when a power on reset
occurs. This flag can only be cleared by writing a 1. Writing a 0 has
no effect.
0 = Power on reset has not yet occurred
Address Offset: $0002
Bit 7 6543210
Read:
TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0
Write:
Reset: 00000000
Address Offset: $0003
Bit 7 6543210
Read:
RTIF PORF
0
LOCKIF
LOCK TRACK
SCMIF
SCM
Write:
Reset: 0
(1)
000000
= Unimplemented or reserved
1. PORF set to 1 when a power on reset occurs. Unaffected by non-POR resets.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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