Datasheet

Central Processing Unit (CPU)
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
ASR opr16a
ASR oprx0_xysppc
ASR oprx9 , xysppc
ASR oprx16 , xysppc
ASR [D, xysppc ]
ASR [ oprx16 , xysppc ]
ASRA
ASRB
Arithmetic shift right M
Arithmetic shift right A
Arithmetic shift right B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
77 hh ll
67 xb
67 xb ff
67 xb ee ff
67 xb
67 xb ee ff
47
57
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
BCC rel8 Branch if C clear; if C=0, then
(PC)+2+rel⇒PC; same as BHS
REL 24 rr PPP (branch)
P (no branch)
BCLR opr8a , msk8
BCLR opr16a , msk8
BCLR oprx0_xysppc , msk8
BCLR oprx9 , xysppc , msk8
BCLR oprx16 , xysppc , msk8
Clear bit(s) in M; (M)•(mask byte)⇒M
DIR
EXT
IDX
IDX1
IDX2
4D dd mm
1D hh ll mm
0D xb mm
0D xb ff mm
0D xb ee ff mm
rPwO
rPwP
rPwO
rPwP
frPwPO
BCS rel8 Branch if C set; if C=1, then
(PC)+2+rel⇒PC; same as BLO
REL 25 rr PPP (branch)
P (no branch)
BEQ rel8 Branch if equal; if Z=1, then
(PC)+2+rel⇒PC
REL 27 rr PPP (branch)
P (no branch)
BGE rel8 Branch if ≥ 0, signed; if N⊕V=0, then
(PC)+2+rel⇒PC
REL 2C rr PPP (branch)
P (no branch)
BGND Enter background debug mode INH 00 VfPPP
BGT
rel8 Branch if > 0, signed; if Z | (N⊕V)=0,
then (PC)+2+rel⇒PC
REL 2E rr PPP (branch)
P (no branch)
BHI rel8 Branch if higher, unsigned; if C | Z=0,
then (PC)+2+rel⇒PC
REL 22 rr PPP (branch)
P (no branch)
BHS rel8 Branch if higher or same, unsigned; if
C=0, then (PC)+2+rel⇒PC; same as
BCC
REL 24 rr PPP (branch)
P (no branch)
BITA #
opr8i
BITA opr8a
BITA opr16a
BITA oprx0_xysppc
BITA oprx9 , xysppc
BITA oprx16 , xysppc
BITA [D, xysppc ]
BITA [ oprx16 , xysppc ]
Bit test A; (A)•(M) or (A)•imm IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
85 ii
95 dd
B5 hh ll
A5 xb
A5 xb ff
A5 xb ee ff
A5 xb
A5 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
BITB # opr8i
BITB opr8a
BITB opr16a
BITB oprx0_xysppc
BITB oprx9 , xysppc
BITB oprx16 , xysppc
BITB [D, xysppc ]
BITB [ oprx16 , xysppc ]
Bit test B; (B)•(M) or (B)•imm IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C5 ii
D5 dd
F5 hh ll
E5 xb
E5 xb ff
E5 xb ee ff
E5 xb
E5 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
BLE rel8 Branch if ≤ 0, signed; if Z | (N⊕V)=1,
then (PC)+2+rel⇒PC
REL 2F rr PPP (branch)
P (no branch)
BLO rel8 Branch if lower, unsigned; if C=1, then
(PC)+2+rel⇒PC; same as BCS
REL 25 rr PPP (branch)
P (no branch)
BLS rel8 Branch if lower or same, unsigned; if
C | Z=1, then (PC)+2+rel⇒PC
REL 23 rr PPP (branch)
P (no branch)
BLT rel8 Branch if < 0, signed; if N⊕V=1, then
(PC)+2+rel⇒PC
REL 2D rr PPP (branch)
P (no branch)
BMI rel8 Branch if minus; if N=1, then
(PC)+2+rel⇒PC
REL 2B rr PPP (branch)
P (no branch)
BNE rel8 Branch if not equal to 0; if Z=0, then
(PC)+2+rel⇒PC
REL 26 rr PPP (branch)
P (no branch)
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
Cb7 b0
––––∆∆∆∆
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––––∆∆0–
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––––∆∆0–
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Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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