Datasheet

Clocks and Reset Generator (CRG)
Register Descriptions
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Figure 40 Clock Chain for RTI
Register Descriptions
NOTE: All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
CRG Synthesizer
Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the
PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the PLLCLK from the reference frequency by 2 x N, where
N is SYNR+1.
CAUTION: PLLCLK should not exceed the maximum operating system frequency
OSCCLK
RTR[6:4]
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
COUNTER (RTR[3:0])
4-BIT MODULUS
÷ 1024
RTI TIMEOUT
PLLCLK 2xOSCCLKx
SYNR 1+()
REFDV 1+()
-----------------------------------
=
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...