Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Clocks and Reset Generator (CRG)
Functional Description
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Figure 37 Clock Chain for COP
Power-On detect
sequence
Figure 38 and Figure 39 show the power-up sequence for cases when
the RESET
pin is tied to VDD and when the RESET pin is held low.
Figure 38 RESET
pin tied to VDD (by a pull-up resistor)
OSCCLK
CR[2:0]
COP TIMEOUT
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 4
÷ 4
÷ 2
÷ 4
÷ 2
÷ 16384
÷ 4
CR[2:0]
RESET
Internal POR
128 SYSCLK
64 SYSCLK
Internal RESET
8192 SYSCLK
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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