Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
static period). In the case of POR, the reset recovery sequence starts in
self clock mode. The internal reset recovery sequence then drives
RESET
low for 128 SYSCLK cycles and releases the drive to allow
RESET
to rise. 64 SYSCLK cycles later this circuit samples the RESET
pin to see if it has risen to a logic one level. If RESET
is low at this point,
the reset is assumed to be coming from an external request and the
internally latched states of the COP timeout and crystal monitor failure
are cleared so the normal reset vector ($FFFE:FFFF) is taken when
RESET
is finally released. If RESET is high after this 64 cycle delay, the
reset source is tentatively assumed to be either a COP failure or a crystal
monitor failure. If the internally latched state of the crystal monitor fail
circuit is true, processing begins by fetching the crystal monitor vector
($FFFC:FFFD). If no crystal monitor failure is indicated, and the latched
state of the COP timeout is true, processing begins by fetching the COP
vector ($FFFA:FFFB). If neither crystal monitor fail nor COP timeout are
pending, processing begins by fetching the normal reset vector
($FFFE:FFFF).
Computer
Operating
Properly (COP)
Watchdog
The COP watchdog enables the user to check that a program is running
and sequencing properly. When the COP is being used, software is
responsible for keeping a free running watchdog timer from timing out. If
the watchdog timer times out it is an indication that the software is no
longer being executed in the intended sequence; thus a system reset is
initiated. The watchdog timer runs with OSCCLK. Three control bits in
the COPCTL register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this
order) to the ARMCOP register during the selected time-out period.
Once this is done, the internal COP counter resets to the start of a new
time-out period. If the program fails to do this the part will reset. Also, if
any value other than $55 or $AA is written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL
register. In this mode, writes to the ARMCOP register to clear the COP
timer must occur in the last 25% of the selected time-out period. A
premature write will immediately reset the part. See Figure 37.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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