Datasheet

Clocks and Reset Generator (CRG)
Functional Description
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Figure 36 System clocks phase relationship
External clock
mode
The oscillator can be completely bypassed and turned off by selecting
an external clock source instead. The crystal monitor, PLL, RTI, COP
and OSCCLK are driven by this external clock instead of the output of
the oscillator. This mode is latched during reset by driving the XCLKS
(external clock select) input low while the RESET pin is low.
System Reset
Generator
The reset sequence is initiated by any of the following events:
• Low level is detected at the RESET
pin
• COP watchdog timer times out
• Power-on is detected
• Crystal monitor failure is detected and the SCME bit is cleared
External circuitry connected to the RESET
pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic one within 64 SYSCLK cycles after the low drive is released.
Upon detection of any reset, an internal circuit drives the RESET
pin low
and a clocked reset sequence controls when the MCU can begin normal
processing.
NOTE: Entry into reset is asynchronous and does not require a clock. However,
the MCU cannot sequence out of reset without a system clock.
In the case of a crystal monitor failure, the MCU remains static until
crystal activity and a stable amplitude signal are detected before the
reset recovery sequence starts (RESET
is driven low throughout this
CORE CLOCK
CLK3
clk23
PERIPHERALS
CLOCK
clk24
ECLK
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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