Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
System Clocks
Generator
Figure 35 Clock Generator
The clock generator creates the system clocks used in the MCU. The
peripheral and memory modules use CLK3. The CLK23 signal is used
to generate the clock visible at the ECLK pin. The CLK24 signal is the
clock for the STAR12 Core. Figure 36 shows the ideal phase
relationships of the system clocks.
PLL clock mode is selected with PLLSEL bit in the CLKSEL register.
When selected, the PLL output clock drives SYSCLK for the main
system including the CPU and peripherals. The PLL cannot be turned off
if the PLL clock is selected. When PLLSEL is changed, it takes several
cycles to make the transition. During the transition, all clocks freeze and
CPU activity ceases.
OSCILLATOR
PHASE
LOCK
LOOP
EXTAL
XTAL
SYSCLK
RTI
OSCCLK
OSCCLK
PLLCLK
CLOCK PHASE
GENERATOR
CLK23
CLK3
CRYSTAL
MONITOR
1
0
PLLSEL
÷2
CLK24
COP
OSCCLK
CRG
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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