Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Clocks and Reset Generator (CRG)
Functional Description
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Figure 34 Crystal loss, stop and startup sequence
MCU continues
operation in
self clock mode
Interrupt
?
Clock
?
SCME=1
?
Count 8192
OSCCLK
Count 8192
SCM Cycles
Assert
SCM, SCMIF
Clocks are
released
Wait for
clock
MCU resumes
normal
operation
CPU executes
STOP instruction
Power on
detected
Clock
failure
MCU resets
CME=1
?
&
SCME=0
STOP mode
YES
NO
NO
NO
YES
NO
YES
NO
Clock
?
YES
YES
NO
Clock
?
YES
NO
Count 8192
SCM cycles
Clock
?
YES
NO
Deassert SCM
Clocks resume
normal
operation
MCU resets
CME=1
?
&
SCME=0
YES
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...