Datasheet

Clocks and Reset Generator (CRG)
Functional Description
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Startup Counter. When the presence of an external clock is detected, the
SCM flag is cleared. This sets the self-clock interrupt flag and if enabled
by the SCMIE bit, the self-clock mode interrupt is requested. Upon
leaving self-clock mode, PLLSEL is restored to its value before the loss
of crystal clock, and the system clock returns to its previous frequency.
If AUTO and PLLSEL were set before the crystal clock loss, the system
clock ramps-up and the PLL locks at the previously selected frequency.
To prevent PLL operation when the external clock frequency comes
back, the software should clear the PLLSEL bit while running in
self-clock mode.
Upon exiting STOP with an external reset, the MCU remains in reset
until the Startup counter reaches the end of the 8192 OSCCLK cycles.
See Figure 33.
Figure 33 STOP Exit and Fast STOP Recovery
Crystal Monitor Fail
OSCCLK
self-clock
PLLSEL Restore PLLSEL
SYSCLK PLLCLK (SCM) Restore PLLCLK or OSCCLK
STOP
Startup counter
0 --> 8192
(Clocked by SYSCLK)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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