Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Figure 32 Crystal Clock Loss during Normal Operation
STOP mode If CME bit is cleared, the MCU goes into STOP mode when a STOP
instruction is executed. STOP mode can then be exited with an external
asynchronous interrupt or an external reset. The clock generator
remains static until crystal activity is detected. The MCU will continue
activity after the Startup Counter completes 8192 OSCCLK cycles.
If CME bit is set and SCME bit is cleared, a crystal monitor failure is
detected when a STOP instruction is executed and the MCU resets. The
MCU remains in reset until the Startup counter completes counting 8192
OSCCLK cycles.
If CME and SCME bits are set, the MCU goes into STOP mode when a
STOP instruction is executed. STOP mode can then be exited with an
external asynchronous interrupt or an external reset.
Upon exiting STOP with an interrupt, the MCU goes into self-clock mode
in the absence of a stable oscillator and the output of the PLLSEL bit is
forced high. The MCU recovers from STOP in self-clock mode, with both
SCM and SCMIF bits set, to indicate it is not operating at the desired
frequency. The VCO supplies the self clock mode frequency to the
self-clock
PLLSEL Restore PLLSEL
SYSCLK
PLLCLK (self-clock)
Restore OSCCLK
OSCCLK
Crystal Monitor Fail
OSCCLK
static
PLLSEL = 0
SYSCLK
PLLCLK (self-clock)
Restore PLLCLK
PLLCLK
PLLSEL = 1
0 --> 8192
(Clocked by SYSCLK)
Startup counter
0 --> 8192
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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