Datasheet

Clocks and Reset Generator (CRG)
Functional Description
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
counts 8192 crystal clock cycles and at the end of the start up count the
MCU completes its internal reset sequence.
If the SCME and CME bits are set, and a loss of crystal clock is detected
by the crystal monitor circuit, the PLL VCO clock at its minimum
frequency is provided as the system clock (self clock mode), allowing the
MCU to continue operating. In self-clock mode, PLLON and PLLSEL
outputs are forced high. The SCM flag in the CRGFLG register indicates
that the MCU is running in self-clock mode. A change of this flag sets the
self-clock interrupt flag and if enabled by the SCMIE bit, the self-clock
mode interrupt is requested.
Each time the Startup Counter reaches the end of the count, a check of
the crystal monitor status is performed. When the presence of an
external clock is detected, the MCU leaves self-clock mode and the SCM
flag is cleared. This also sets the self-clock interrupt flag. Upon leaving
self-clock mode, PLLSEL is restored to its value before the crystal clock
loss, and the system clock returns to its previous frequency. If AUTO and
PLLSEL were set before the crystal clock loss, the system clock
ramps-up and the PLL locks at the previously selected frequency. See
Figure 32.
NOTE: There is a delay between the loss of crystal clock and its detection by the
crystal monitor. If the MCU is clocked by OSCCLK and the PLL is not
used there is a potential for runaway code by the CPU before self clock
mode is activated. The best policy is to clear SCME when the MCU is
clocked by OSCCLK to get a monitor reset. The COP watch dog should
always be enabled in order to reset the MCU in case of a code runaway
situation.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...