Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Figure 31 No Clock at Power-On
Crystal Clock Loss
during Normal
Operation
The self-clock mode enable bit, SCME, the crystal monitor enable bit,
CME, and the PLLSEL bit determine how the MCU responds to an
external crystal clock loss.
If the CME bit is cleared when a loss of crystal clock happens, the MCU
goes static if PLLSEL is cleared, or it drifts to self clock mode if PLLSEL
is set but the self clock mode status will not be indicated.
If the SCME bit is cleared, with CME set, and a loss of crystal clock is
detected by the crystal monitor circuit, the MCU resets. The MCU
remains static until crystal activity is detected. Then the Startup Counter
self-clock
VDD
Power-On Detector
Crystal Monitor Fail
OSCCLK
Reset
PLLSEL
Reset: PLLSEL = 0
SYSCLK SCM OSCCLK
SYSCLK PLLCLK (Software check of self-clock Flag) OSCCLK
(Slow crystal)
(Slow crystal)
Startup counter
0 --> 8192
(Clocked by SYSCLK)
0 --> 8192
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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