Datasheet

Clocks and Reset Generator (CRG)
Functional Description
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
high. After the Startup Counter reaches the end of the count, 8192 self
clock mode cycles, reset is released. At this time, if the crystal monitor
indicates the presence of an external clock, self-clock mode is
de-asserted and the MCU exits reset normally, using OSCCLK clock. In
case the crystal start-up time is longer than the initial count of 8192 self
clock mode cycles, or in the absence of an external clock, the MCU
leaves the reset state in self-clock mode. Both SCM and SCMIF bits are
set indicating the MCU is not operating at the desired frequency. Each
time the Startup Counter reaches the end of the count, a check of the
crystal monitor status is performed. When the presence of an external
clock is detected, the SCM flag is cleared. This sets the self-clock
interrupt flag and if enabled by the SCMIE bit, the self-clock mode
interrupt is requested.
See Figure 31.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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