Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
The PLL also can operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below the
maximum system frequency, f
sys,
and require fast start-up. The following
conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit should be
set to configure the filter in acquisition mode.
• Before entering tracking mode (ACQ = 0), software must wait a
given time, t
acq
, after turning on the PLL by setting PLLON in the
PLL control register, or wait until TRACK bit gets set.
• Software must wait a given time, t
al
, after entering tracking mode
before selecting the PLLCLK as the SYSCLK clock source
(PLLSEL = 1).
Self clock mode The VCO has a minimum operating frequency, f
VCOMIN
. If the crystal
frequency is not available due to a failure or due to long crystal start-up
time, the MCU system clock can be supplied by the VCO. This mode of
operation is called Self-Clock mode. See Crystal loss, stop and startup
for more information.
Crystal loss, stop
and startup
The lack of external clocks can occur in three configurations, which are
described below:
1. At Power-On Reset.
2. During normal clock operation.
3. In the STOP exit sequence.
Crystal startup at
Power-On
Any reset sets the Crystal Monitor Enable bit, CME, the PLLON bit, and
the self clock mode enable bit, SCME. Therefore, if the MCU is powered
up without an external clock, self-clock mode is activated.
During a normal power up sequence without an external clock, after the
POR pulse falling edge, the VCO supplies the self-clock mode frequency
to the 14-stage Startup Counter as the output of the PLLSEL bit is forced
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...