Datasheet

Clocks and Reset Generator (CRG)
Functional Description
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Phase Locked
Loop (PLL)
Figure 30 PLL Functional Diagram
The PLL is used to run the MCU from a different time base than the
incoming crystal value. For increased flexibility, the crystal clock can be
divided in a range of 1 to 16 to generate the reference frequency. This
offers a finer multiplication granularity. The PLL can multiply this
reference clock by a multiple of 2, 4, 6, ... 126,128 based on the SYNR
register.
PLLCLK = 2 x OSCCLK x [SYNR + 1] / [REFDV + 1]
NOTE: Although it is possible to set the two dividers to command a very high
clock frequency, do not exceed the specified bus frequency limit for the
MCU.
The PLL is a frequency generator that operates in either acquisition
mode or tracking mode, depending on the difference between the output
frequency and the target frequency. The PLL can change between
acquisition and tracking modes either automatically or manually.
REDUCED
CONSUMPTION
OSCILLATOR
EXTAL
XTAL
OSCCLK
PLLCLK
REFERENCE
PROGRAMMABLE
DIVIDER
PDET
PHASE
DETECTOR
REFDV <3:0>
LOOP
PROGRAMMABLE
DIVIDER
SYN <5:0>
CPUMP VCO
LOCK
LOOP
FILTER
XFC
PAD
UP
DOWN
LOCK
DETECTOR
REFERENCE
FEEDBACK
VDDPLL
VDDPLL/VSSPLL
CRYSTAL
MONITOR
VDDPLL/VSSPLL
VDD/VSS
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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