Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
The crystal oscillator is equipped with a feedback system which does not
waste current generating harmonics. Its configuration is “Colpitts
oscillator with translated ground”. The transconductor used is driven by
a current source under the control of a peak detector which will measure
the amplitude of the AC signal appearing on EXTAL node in order to
implement an Amplitude Limitation Control (ALC) loop. The ALC loop is
in charge of reducing the quiescent current in the transconductor as a
result of an increase in the peak-to-peak oscillation amplitude.
Crystal Monitor
(CM)
The crystal monitor circuit is based on an internal resistor-capacitor (RC)
time delay so that it can operate without any MCU clocks. If no clock
edges are detected within this RC time delay, the crystal monitor
indicates failure which asserts self clock mode or generates a system
reset depending on the state of SCME bit. If the crystal monitor is
disabled or the presence of clocks are detected no failure is
indicated.The crystal monitor function is enabled/disabled by the CME
control bit. See Register Descriptions.
Startup counter The Startup Counter is a 14-stage ripple free-running counter that
counts system clock cycles to ensure proper oscillator start up recovery.
It is initialized at power on, stop mode, and any failure indicated by the
crystal monitor when SCME bit is cleared. See Crystal loss, stop and
startup for more information.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...