Datasheet

Clocks and Reset Generator (CRG)
Functional Description
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
NOTE: Register Address = Module Address + Base Address + Address Offset
The Module Address is determined at the MCU level.
The Address Offset is determined by a switch in the i/o of the module. If
the switch is set, the address offset is four bytes, and if it is clear there
is no offset.
Functional Description
Oscillator (OSC) The oscillator block has two external pins, EXTAL and XTAL. See
Register Descriptions. The oscillator input pin, EXTAL, is intended to be
connected to either a crystal or an external clock source. The XTAL pin
is an output signal that provides crystal circuit feedback and can be
buffered to drive other devices with same voltage amplitude. It is also
used as an input pin during test when the MCU has an external clock
source.
A buffered EXTAL signal, OSCCLK, becomes the internal reference
clock. The oscillator is enabled based on the PSTP bit, and the STOP
condition. The oscillator is disabled when the part is in STOP mode
except when Pseudo-Stop mode is enabled. See Register Descriptions
for detailed bit descriptions.
To improve noise immunity, the OSC is powered by the VDDPLL and
VSSPLL power supply pins.
Table 45 CRG Register Address Summary
Register SYN REFDV CTFLG CRGFLG CRGINT CLKSEL
Base
Address
$0000 $0001 $0002 $0003 $0004 $0005
Register PLLCTL RTICTL COPCTL FORBYP CTCTL ARMCOP
Base
Address
$0006 $0007 $0008 $0009 $000A $000B
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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