Datasheet

Central Processing Unit (CPU)
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
Instruction Set Summary
The following table defines the special characters used to describe the
effects of instruction execution on the status bits in the condition codes
register (SXHINZVC column).
Table 5 Condition Code Changes
Special Character Description
- Status bit not affected by operation.
0 Status bit cleared by operation.
1 Status bit set by operation.
Status bit affected by operation.
Status bit may be cleared or remain set, but is not set
by operation.
Status bit may be set or remain cleared, but the final
state is not defined.
?
Status bit may be changed by operation but the final
state is not defined.
! Status bit used for a special purpose.
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
ABA Add B to A; (A)+(B)⇒A INH 18 06
OO
ABX Add B to X; (X)+(B)⇒X; assembles as
LEAX B,X
IDX 1A E5
Pf
ABY Add B to Y; (Y)+(B)⇒Y; assembles as
LEAY B,Y
IDX 19 ED
Pf
ADCA #
opr8i
ADCA opr8a
ADCA opr16a
ADCA oprx0_xysppc
ADCA oprx9 , xysppc
ADCA oprx16 , xysppc
ADCA [D, xysppc ]
ADCA [ oprx16 , xysppc ]
Add with carry to A; (A)+(M)+C⇒A or
(A)+imm+C⇒A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
89 ii
99 dd
B9 hh ll
A9 xb
A9 xb ff
A9 xb ee ff
A9 xb
A9 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
– – ∆ – ∆ ∆ ∆ ∆
– – – – – – – –
– – – – – – – –
––∆ – ∆∆∆∆
||
>
||
>
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...