Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Port Integration Module
Low Power Options
MC9S12DP256 — Revision 1.1
Port Integration Module
Figure 28 Pulse Illustration
Port H Port H offers 8 I/O ports with the same interrupt features as port P.
Port J This port is associated with the fifth CAN and the IIC module. In all
modes, port J pins PJ[7:6] and PJ[1:0] can be used for either general
purpose I/O, or with the CAN and IIC subsystems. Pins PJ6 and PJ7 are
shared between the CAN4 and the IIC module. If CAN4 is enabled the
pins become CAN transmit and receive pins. If IIC is enabled and CAN4
is disabled, the pins become IIC open-drain output pins. During reset,
port J pins are configured as inputs with pull-up.
Port J offers 4 I/O ports with the same interrupt features as port P.
Low Power Options
Run Mode No low power options exist for this module in run mode.
Wait Mode No low power options exist for this module in wait mode.
Stop Mode All clocks are stopped. There are however asynchronous paths to
generate interrupts from STOP on port P, H and J.
t
pulse
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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