Datasheet

Port Integration Module
MC9S12DP256 — Revision 1.1
Port Integration Module
consecutive samples have to be either low or high in order to detect a
valid low or high input.
The filters are continuously clocked by the bus clock in RUN and WAIT
mode. In STOP mode the clock is generated by a single RC oscillator in
the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin:
Active level at the input as defined by the port polarity select register
(PPS)
and port interrupt enabled (PIE=1)
and port interrupt flag not set (PIF=0).
Figure 27 Interrupt Glitch Filter on Port P, H and J
Table 43 Pulse Detection Criteria
Pulse
Mode
STOP
STOP
(1)
1. These values include the spread of the oscillator frequency over temperature,
voltage and process.
t
if
Unit
t
if
Unit
Ignored
t
pulse
<= 3
bus clocks
t
pulse
<= 3.2
µs
Uncertain
3 < t
pulse
< 4
bus clocks
3.2 < t
pulse
< 10
µs
Valid
t
pulse
>= 4
bus clocks
t
pulse
>= 10
µs
Glitch, Filtered out, no Interrupt Flag setting
Valid Pulse, Interrupt flag set
t
ifmin
t
ifmax
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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