Datasheet

Port Integration Module
Functional Description
MC9S12DP256 — Revision 1.1
Port Integration Module
Port S This port is associated with the serial SCI and SPI modules. In all modes,
port S pins PS[7:0] can be used either for general-purpose I/O, or with
the SCI and SPI subsystems. During reset, port S pins are configured as
inputs with pull-up.
Port M This port is associated with the J1850 and 4 CAN modules. In all modes,
port M pins PM[7:0] can be used for either general purpose I/O, or with
the CAN and J1850 subsystems. Pins PM0 and PM1 are shared
between the CAN0 and the BDLC (J1850) module. If CAN0 is enabled
the pins become CAN transmit and receive pins. If BLDC is enabled and
CAN0 is disabled, pins become active BDLC transmit and receive pins.
During reset, port M pins are configured as high-impedance inputs.
Port P This port is associated with the PWM and 2 SPI modules. In all modes,
port P pins PP[7:0] can be used for either general purpose I/O, or with
the PWM and SPI subsystems. The pins are shared between the PWM
channels and the SPI1 and SPI2 modules. If the PWM is enabled the
pins become PWM output channels with the exception of pin 7 which can
be PWM input or output. If SPI1 or SPI2 are enabled and PWM is
disabled, the respective pin configuration is determined by several
status bits in the SPI modules. During reset, port P pins are configured
as high-impedance inputs.
Port P offers 8 I/O pins with edge triggered interrupt capability in wired-or
fashion. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per pin basis. All 8 bits/pins
share the same interrupt vector. Interrupts can be used with the pins
configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and
its corresponding port interrupt enable bit are both set.
This external interrupt feature is capable to wake up the CPU when it is
in STOP or WAIT mode.
A digital filter on each pin prevents pulses shorter than a specified time
from generating an interrupt (see Pulse Detection Criteria). Four
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