Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Port Integration Module
MC9S12DP256 — Revision 1.1
Port Integration Module
Data direction
register
This register defines whether the pin is used as an input or an output. If
a peripheral module controls the pin the contents of the data direction
register is ignored.
Figure 26 Illustration of I/O pin functionality
Reduced drive
register
If the port is used as an output the register allows the configuration of the
drive strength.
Pull device enable
register
This register turns on a pull-up or pull-down device. It becomes only
active if the pin is used as an input or as a wired-or output.
Polarity select
register
This register selects either a pull-up or pull-down device if enabled. It
becomes only active if the pin is used as an input. A pull-up device can
be activated if the pin is used as a wired-or output.
Port T This port is associated with the Enhanced Capture Timer module. In all
modes, port T pins PT[7:0] can be used for either general-purpose I/O,
or with the channels of the Enhanced Capture Timer. During reset, port
T pins are configured as high-impedance inputs.
I/O
DDR
MOD
do
obe
mod_en
PT
PTI
1
0
1
1
0
0
PAD
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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