Datasheet

Port Integration Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Port Integration Module
Port J Data
Direction Register
(DDRJ)
Read: Anytime.
Write: Anytime.
This register configures each port J pin as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TxCAN4) and an
input on pin PJ6 (RxCAN4). The IIC forces the I/O state to be an output
or input dependent on the state of the IIC bus if enabled. In these cases
the data direction bits will not change. The DDRJ bits revert to controlling
the I/O direction of a pin when the associated timer output compare is
disabled.
DDRJ[7:6][1:0] — Data Direction Port J
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTJ or PTIJ registers, when changing
the DDRJ register.
Address Offset: $002A
Bit 7 654321Bit 0
Read:
DDRJ7 DDRJ6
0000
DDRJ1 DDRJ0
Write:
Reset: 0 0 –f –f –f –f 0 0
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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