Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x14) 16-Bit 25 MHz I/O number 59

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Table Of Contents

List of Sections
Table of Contents
General Description
- Contents
- Introduction
- Features
- MC9S12DP256 112-Pin Block Diagram
- Ordering Information
Central Processing Unit (CPU)
- Contents
- Introduction
- Programming Model
- Data Types
- Addressing Modes
- Indexed Addressing Modes
- Opcodes and Operands
- Instruction Set Summary
Pinout and Signal Description
- Contents
- MC9S12DP256 Pin Assignments in 112-pin QFP
- Power Supply Pins
- Signal Descriptions
- Port Signals
System Configuration
- Contents
- Introduction
- Modules Variabilities
- MCU Variabilities
Registers
- Contents
- Register Block
Operating Modes
- Contents
- Introduction
- Operating Modes
- Background Debug Mode
- Security
Resource Mapping
- Contents
- Introduction
- Internal Resource Mapping
- Flash EEPROM mapping through internal Memory Expansion
- Miscellaneous System Control Register
- Memory Maps
Bus Control and Input/Output
- Contents
- Introduction
- Detecting Access Type from External Signals
- Stretched Bus Cycles
- PIPE Status Signals
- Registers
Resets and Interrupts
- Contents
- Introduction
- Register Map
- Exception Priority
- Maskable interrupts
- Latching of Interrupts
- Register Descriptions
- Resets
- Effects of Reset
- Register Stacking
Voltage Regulator (VREG)
- Contents
- Overview
- Features
- Block Diagram
- Functional Description
- External Pin Connection
- Reset Initialization
- Modes of Operation
Flash EEPROM 256K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
EEPROM 4K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Interrupt Operation
Port Integration Module
- Contents
- Overview
- Block Diagram
- External Pin Descriptions
- 80 Pin QFP bond-out version
- Register Map
- Register Descriptions
- Reset Initialization
- Functional Description
- Low Power Options
- Interrupt Operation
Clocks and Reset Generator (CRG)
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Interrupt Operation
- Low Power Options
Pulse Width Modulator (PWM)
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Register Descriptions
- Functional Description
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
Enhanced Capture Timer (ECT)
- Contents
- Overview
- Features
- Modes of Operation
- Abbreviations
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Modes of Operation
- Interrupts
- Description of Interrupt Operation
Serial Communications Interface (SCI)
- Contents
- Overview
- Features
- Modes of Operation
- SCI Interface Diagram
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Modes of Operation
- Interrupt Operation
Serial Peripheral Interface (SPI)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Low Power Mode Options
- Errata
- Reset
- Interrupts
Inter-IC Bus (IIC)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- I-Bus Protocol
- Interrupt Operation
- Modes of Operation
- Programming
MSCAN
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Functional Description
- Register Descriptions
- Modes of Operation
- Low Power Options
- Interrupt Operation
Analog to Digital Converter
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Sample Conversion
- General Purpose Input Ports
Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
Background Debug Module (BDM)
- Contents
- Overview
- Interface Signals
- Registers
- Operation
- Modes of Operation
- Low-Power Options
- Interrupt Operation
Breakpoint (BKP) Module
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Descriptions
- Functional Description
- Breakpoint Operating Modes
- Breakpoint Types
- Modes of Operation
- Low Power Options
- Reset Initialization
- Interrupt Operation
- General Purpose I/O Ports
Revision History
- Changes from Rev 1.0 to Rev 1.1
Glossary
Literature Updates
- Literature Distribution Centers
- Customer Focus Center
- Microcontroller Division’s Web Site

Port Integration Module

MC9S12DP256 — Revision 1.1

Port Integration Module

Port H Interrupt

Flag Register

(PIFH)

Read: Anytime.

Write: Anytime.

Each flag is set by an active edge on the associated input pin. This could

be a rising or a falling edge based on the state of the PPSH register. To

clear this flag, write ‘1’ to the corresponding bit in the PIFH register.

Writing a ‘0’ has no effect.

PIFH[7:0] — Interrupt Flags Port H

1 = Active edge on the associated bit has occurred (an interrupt will

occur if the associated enable bit is set).

Writing a ‘1’ clears the associated flag.

0 = No active edge pending.

Writing a ‘0’ has no effect.

Port J I/O

Read: Anytime.

Write: Anytime.

Address Offset: $0027

Bit 7 654321Bit 0

Read:

PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0

Write:

Reset: 00000000

= Reserved or unimplemented

Address Offset: $0028

Bit 7 654321Bit 0

Read:

PTJ7 PTJ6

0000

PTJ1 PTJ0

Write:

CAN: TxCAN4 RxCAN4

IIC: SCL SDA

Reset: 00000000

= Reserved or unimplemented

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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