Datasheet

Port Integration Module
MC9S12DP256 — Revision 1.1
Port Integration Module
Port H Data Direction
Register (DDRH)
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
DDRH[7:0] — Data Direction Port H
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTH or PTIH registers, when changing
the DDRH register.
Port H Reduced Drive
Register (RDRH)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port H output pin as
either full or reduced. If the port is used as input this bit is ignored.
RDRH[7:0] — Reduced Drive Port H
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Address Offset: $0022
Bit 7 654321Bit 0
Read:
DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
Write:
Reset: 00000000
= Reserved or unimplemented
Address Offset: $0023
Bit 7 654321Bit 0
Read:
RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
Write:
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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