Datasheet

Port Integration Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Port Integration Module
Port P Data
Direction Register
(DDRP)
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register
has no effect on the pins.
The PWM forces the I/O state to be an output for each port line
associated with an enabled PWM7–0 channel. Channel 7 can force the
pin to input if the shutdown feature is enabled.
If a SPI module is enabled, the SPI determines the pin direction.
For
details see SPI specification
.
The DDRM bits revert to controlling the I/O direction of a pin when the
associated PWM channel is disabled.
DDRP[7:0] — Data Direction Port P
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTP or PTIP registers, when changing
the DDRP register.
Address Offset: $001A
Bit 7 654321Bit 0
Read:
DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
Write:
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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