Datasheet

Port Integration Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Port Integration Module
Port M Wired-Or
Mode Register
(WOMM)
Read: Anytime.
Write: Anytime.
This register configures the output pins as wired-or. If enabled the output
is driven active low only (open-drain). A logic level of ‘1’ is not driven. It
applies also to the CAN and BDLC outputs and allows a multipoint
connection of several serial modules. This bit has no influence on pins
used as inputs.
WOMM[7:0] — Wired-Or Mode Port M
1 = Output buffers operate as open-drain outputs.
0 = Output buffers operate as push-pull outputs.
Port P I/O Register
(PTP)
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read
returns the value of the port register, otherwise the value at the pins is
Address Offset: $0016
Bit 7 654321Bit 0
Read:
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Write:
Reset: 00000000
= Reserved or unimplemented
Address Offset: $0018
Bit 7 654321Bit 0
Read:
PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
Write:
PWM: PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
SPI: SCK2 SS2
MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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