Datasheet

Port Integration Module
MC9S12DP256 — Revision 1.1
Port Integration Module
This register always reads back the status of the associated pins. This
can also be used to detect overload or short circuit conditions on output
pins.
Port M Data
Direction Register
(DDRM)
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN/BDLC forces the I/O state to be an output for each port line
associated with an enabled output (TxCAN[3:0], TxBDLC). It also forces
the I/O state to be an input for each port line associated with an enabled
input (RxCAN[3:0], RxBDLC). In those cases the data direction bits will
not change.
The DDRM bits revert to controlling the I/O direction of a pin when the
associated peripheral module is disabled.
DDRM[7:0] — Data Direction Port M
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTM or PTIM registers, when changing
the DDRM register.
Address Offset: $0012
Bit 7 654321Bit 0
Read:
DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
Write:
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...