Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Port Integration Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Port Integration Module
Port M I/O
Register (PTM)
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read
returns the value of the port register, otherwise the value at the pins is
read.
The CAN function (TxCAN and RxCAN) takes precedence over the
general purpose I/O function if the associated CAN module is enabled.
See MSCAN section
.
The BDLC function takes precedence over the general purpose I/O
function associated with if enabled.
See Byte Data Link Controller
Module section
.
If both CAN0 and BDLC are enabled the CAN functionality takes
precedence.
Port M Input
Register (PTIM)
Read: Anytime.
Write: Never; writes to this register have no effect.
Address Offset: $0010
Bit 7 654321Bit 0
Read:
PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
Write:
CAN: TxCAN3 RxCAN3 TxCAN2 RxCAN2 TxCAN1 RxCAN1 TxCAN0 RxCAN0
J1850: TxBDLC RxBDLC
Reset: 00000000
= Reserved or unimplemented
Address Offset: $0011
Bit 7 654321Bit 0
Read: PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
Write:
Reset: --------
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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