Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Central Processing Unit (CPU)
Addressing Modes
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
Addressing Modes
Addressing modes determine how the CPU accesses memory locations
to be operated upon. The STAR12 CPU includes all of the addressing
modes of the M68HC11 CPU as well as several new forms of indexed
addressing. Table 3 is a summary of the available addressing modes.
Table 3 M68HC12 Addressing Mode Summary
Addressing Mode Source Format Abbreviation Description
Inherent
INST
(no externally supplied
operands)
INH Operands (if any) are in CPU registers
Immediate
INST #
opr8i
or
INST #
opr16i
IMM
Operand is included in instruction stream
8- or 16-bit size implied by context
Direct INST
opr8a
DIR
Operand is the lower 8-bits of an address in the
range $0000 – $00FF
Extended INST
opr16a
EXT Operand is a 16-bit address
Relative
INST
rel8
or
INST
rel16
REL
An 8-bit or 16-bit relative offset from the current
pc is supplied in the instruction
Indexed
(5-bit offset)
INST
oprx5
,
xysp
IDX 5-bit signed constant offset from x, y, sp, or pc
Indexed
(auto pre-decrement)
INST
oprx3
,
–xys
IDX Auto pre-decrement x, y, or sp by 1 ~ 8
Indexed
(auto pre-increment)
INST
oprx3,+xys
IDX Auto pre-increment x, y, or sp by 1 ~ 8
Indexed
(auto post-
decrement)
INST
oprx3
,
xys–
IDX Auto post-decrement x, y, or sp by 1 ~ 8
Indexed
(auto
post-increment)
INST
oprx3
,
xys+
IDX Auto post-increment x, y, or sp by 1 ~ 8
Indexed
(accumulator offset)
INST
abd
,
xysp
IDX
Indexed with 8-bit (A or B) or 16-bit (D)
accumulator offset from x, y, sp, or pc
Indexed
(9-bit offset)
INST
oprx9
,
xysp
IDX1
9-bit signed constant offset from x, y, sp, or pc
(lower 8-bits of offset in one extension byte)
Indexed
(16-bit offset)
INST
oprx16
,
xysp
IDX2
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Indexed-Indirect
(16-bit offset)
INST [
oprx16
,
xysp
] [IDX2]
Pointer to operand is found at...
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Indexed-Indirect
(D accumulator
offset)
INST [D,
xysp
] [D,IDX]
Pointer to operand is found at...
x, y, sp, or pc plus the value in D
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