Datasheet

Port Integration Module
MC9S12DP256 — Revision 1.1
Port Integration Module
This register configures each port S pin as either input or output.
If SPI is enabled, the SPI determines the pin direction.
For details see
Serial Peripheral Interface (SPI) section .
If the associated SCI transmit or receive channel is enabled this register
has no effect on the pins. The pin is forced to be an output if a SCI
transmit channel is enabled, it is forced to be an input if the SCI receive
channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the
associated channel is disabled.
DDRS[7:0] — Data Direction Port S
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTS or PTIS registers, when changing
the DDRS register.
Port S Reduced
Drive Register
(RDRS)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port S output pin as
either full or reduced. If the port is used as input this bit is ignored.
RDRS[7:0] — Reduced Drive Port S
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Address Offset: $000B
Bit 7 654321Bit 0
Read:
RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Write:
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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