Datasheet

Port Integration Module
MC9S12DP256 — Revision 1.1
Port Integration Module
Register Descriptions
The following table summarizes the effect on the various configuration
bits, data direction (DDR), output level (I/O), reduced drive (RDR), pull
enable (PE), polarity select (PS) and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt
is enabled.
2. Select either a pull-up or pull-down device if PE is active.
NOTE: All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
Table 42 Pin Configuration Summary
DDR IO RDR PE PS
IE
(1)
Function Pull Device Interrupt
0XX0X0 Input Disabled Disabled
0 X X 1 0 0 Input Pull Up Disabled
0 X X 1 1 0 Input Pull Down Disabled
0 X X 0 0 1 Input Disabled falling edge
0 X X 0 1 1 Input Disabled rising edge
0 X X 1 0 1 Input Pull Up falling edge
0 X X 1 1 1 Input Pull Down rising edge
1 0 0 X X 0 Output, full drive to 0 Disabled Disabled
1 1 0 X X 0 Output, full drive to 1 Disabled Disabled
1 0 1 X X 0 Output, reduced drive to 0 Disabled Disabled
1 1 1 X X 0 Output, reduced drive to 1 Disabled Disabled
1 0 0 X 0 1 Output, full drive to 0 Disabled falling edge
1 1 0 X 1 1 Output, full drive to 1 Disabled rising edge
1 0 1 X 0 1 Output, reduced drive to 0 Disabled falling edge
1 1 1 X 1 1 Output, reduced drive to 1 Disabled rising edge
1. Applicable only on port P, H and J.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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