Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Port Integration Module
Block Diagram
MC9S12DP256 — Revision 1.1
Port Integration Module
Block Diagram
Figure 24 PIM_9DP256 Block Diagram
Port T
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
Timer
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
Port P
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PWM
PW0
PW1
PW2
PW3
PW4
PW5
PW6
PW7
Port S
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
RXD
TXD
RXD
TXD
SDI/MISO
SDO/MOSI
SCK
SS
SCI0
SCI1
SPI0
Port H
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
Port J
PJ0
PJ1
PJ6
PJ7
Port M
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
CAN3
TxCAN
RxCAN
CAN1
TxCAN
RxCAN
CAN2
TxCAN
RxCAN
CAN0
TxCAN
RxCAN
BDLC
TxB
RxB
IIC
SDA
SCL
Port Integration Module
IP-Bus
INTJ
INTH
Interrupt Logic
CAN4
TxCAN
RxCAN
Interrupt Logic
SDI/MISO
SDO/MOSI
SCK
SS
SPI1
Interrupt Logic
SDI/MISO
SDO/MOSI
SCK
SS
SPI2
INTP
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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