Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Port Integration Module
MC9S12DP256 — Revision 1.1
Port Integration Module
associated with the fifth CAN module and the IIC interface
1
. Ports P, H
and J can also be used as external interrupt sources.
Each I/O pin can be configured by several registers: Input/output
selection, drive strength reduction, enable and select of pull resistors,
interrupt enable and status flags.
The port integration module is device dependant which is reflected in its
naming.
A standard port has the following minimum features:
• Input/output selection
• 5V output drive with two selectable drive strength
• 5V digital and analog input
• Input with selectable pull-up or pull-down device
Optional features:
• Open drain for wired-or connections
• Interrupt inputs with glitch filtering
1. The port control register addresses are allocated in the order of their most likely occurrence,
i.e. almost all STAR12 derivatives will have a timer port, and a very limited number will have a
IIC module. This allows best consistency in the address allocation.
Table 41 Port Reset State and Priority Summary
Port
Reset States
Priority
Data
Direction
Pull Mode Red. Drive
Wired-Or
Mode
Inter-
rupt
T input hiz disabled n/a n/a ECT > GPIO
S input pull-up disabled disabled n/a SCI, SPI > GPIO
M input hiz disabled disabled n/a CAN > BDLC > GPIO
P input hiz disabled n/a disabled PWM > SPI > GPIO
H input hiz disabled n/a disabled GPIO
J input pull-up disabled n/a disabled CAN > IIC > GPIO
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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