Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

EEPROM 4K
Interrupt Operation
MC9S12DP256 — Revision 1.1
EEPROM 4K
Interrupt Operation
This module can generate an interrupt when all commands are
completed or the command buffer is empty.
Interrupt Sources
NOTE:
Vector addresses and their relative interrupt priority are determined at
the MCU level.
Recovery from
STOP or WAIT
The module can recover the part from WAIT, if the interrupts are
enabled.
There is no capability to recover from STOP.
Table 40 EEPROM 4K Interrupt Sources
Interrupt Source
Interrupt
Flag
Local Enable
Global (CCR)
Mask
EEPROM Address,
Data and Command
Buffers empty
CBEIF
EEPROM
CBEIE I Bit
All Commands are
completed
CCIF
EEPROM
CCIE I Bit
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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