Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Central Processing Unit (CPU)
Programming Model
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
Index registers
X and Y are used for indexed addressing mode. In the
indexed addressing mode, the contents of a 16-bit index register are
added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator
to form the effective address of the operand to be used in the instruction.
Stack and Memory Layout
Figure 2 Stack and Memory Layout
Stack pointer
(SP) points to the last stack location used. The STAR12
CPU supports an automatic program stack that is used to save system
context during subroutine calls and interrupts, and can also be used for
HIGHER ADDRESSES
LOWER ADDRESSES
RTN
L
RTN
H
Y
L
Y
H
X
L
X
H
A
B
CCR
SP BEFORE INTERRUPT
SP AFTER INTERRUPT
STACK UPON ENTRY TO SERVICE ROUTINE
IF SP WAS ODD BEFORE INTERRUPT
STACK UPON ENTRY TO SERVICE ROUTINE
IF SP WAS EVEN BEFORE INTERRUPT
SP + 8 RTN
L
SP + 9 SP + 9
SP + 10
SP + 6 Y
L
RTN
H
SP + 7 SP + 7 RTN
H
RTN
L
SP + 8
SP + 4 X
L
Y
H
SP + 5 SP + 5 Y
H
Y
L
SP + 6
SP + 2 A X
H
SP + 3 SP + 3 X
H
X
L
SP + 4
SP CCR B SP + 1 SP + 1 B A SP + 2
SP – 2 SP – 1 SP – CCR SP
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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