Datasheet

EEPROM 4K
MC9S12DP256 — Revision 1.1
EEPROM 4K
machines for the EEPROM.
For frequencies of OSCCLK > 12.8MHz the Prescaler bit FDIV8 must
be turned on.
ECLKDIV must be chosen such that the following equation is valid.
If FDIV8 == 1 then CLK = OSCCLK / 8, else CLK = OSCCLK
ECLKDIV = INT (CLK[KHz] / 200KHz)
The clock to the EEPROM timing control is therefore:
ECLK = CLK / (EDIV[5:0] + 1)
150KHz < ECLK <= 200KHz
For example, if OSCCLK = 950KHz, ECLKDIV should be set to 4 and
PRDIV8 set to 0. The resulting ECLK is 190KHz. As a result the
EEPROM timings are increased by:
(200 - 190) / 200 x 100% = 5%
Remark: INT means rounding towards 0.
Example: INT(950KHz/200KHz) = 4.
WARNING: Programming the EEPROM with OSCCLK < 500KHz should be
avoided. Setting ECLKDIV to a value such that ECLK < 150KHz can
destroy the EEPROM due to overstress. Setting ECLKDIV to a value
such that ECLK > 200KHz can result in improperly programmed
memory cells.
NOTE: Command execution time will increase proportionally with the period of
ECLK.
Table 36 Example ECLKDIV settings
Oscillator
Frequency
PRDIV EDIV[5:0]
ECLK
Frequency
ECLK
Period
1.0MHz 0 000100 200KHz 5us
2.0MHz 0 001001 200KHz 5us
4.0MHz 0 010011 200KHz 5us
8.0MHz 0 100111 200KHz 5us
16.0MHz 1 001001 200KHz 5us
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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