Datasheet

EEPROM 4K
Register Descriptions
MC9S12DP256 — Revision 1.1
EEPROM 4K
Register Descriptions
NOTE: All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
ECLKDIV Ñ
EEPROM Clock
Divider Register.
Read: Anytime
Write: Once in normal modes, anytime in special modes
EDIVLD — EEPROM Clock Divider Loaded
This bit is set when the ECLKDIV register is written to. If this bit is “0”
the register has not been written since the last reset. Trying to
program or erase the EEPROM without having written to this register
previously will result in an access error and the command will not be
executed.
1 = Register has been written to since the last reset.
0 = Register has not been written to since the last reset.
PRDIV8 — Enable Prescaler by 8
1 = Enables a prescaler by 8 before feeding into the ECLKDIV
divider.
0 = OSCCLK is directly fed into the ECLKDIV divider.
EDIV[5:0] — EEPROM Clock Divider
The combination of FDIV8 and EDIV[5:0] is used to divide the
oscillator clock down to a frequency of 150KHz - 200KHz. This
resulting clock, ECLK, is used to drive the program and erase state
Address Offset: $0000
Bit 7 654321Bit 0
Read: EDIVLD
PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
Write:
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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