Datasheet

EEPROM 4K
MC9S12DP256 — Revision 1.1
EEPROM 4K
NOTE: Register Address = Base Address + Address Offset, where the Base
Address is defined at the MCU level and the Address Offset is defined
at the module level.
Functional Description
All internal program and erase timings are handled by a state machine.
The timebase is derived from the oscillator clock OSCCLK via a
programmable down counter. The command register as well as the
associated address and data registers operate as a buffer and a register
(2-stage FIFO), so that a new command along with the necessary data
and address can be stored to the buffers while the previous command is
still in progress. Buffers empty situation as well as command completion
are signalled by flags in the status register. Interrupts will be generated
if enabled.
Program and
Erase Procedures
Prior to issuing any program or erase commands it is first necessary to
program the ECLKDIV register to divide the oscillator clock to within the
150KHz to 200KHz range. Program and erase commands will not
function if this register has not been initialized. See ECLKDIV register
description for further details.
A Command State Machine is used to supervise the command
sequence.
The CBEIF flag should be tested to ensure that the address, data and
command buffers are empty. If so, the command sequence can be
started. The 3-step command sequence must be strictly adhered to and
no intermediate writes to EEPROM registers are permitted between the
3 steps. The command sequence is as follows:
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