Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

EEPROM 4K
Block Diagram
MC9S12DP256 — Revision 1.1
EEPROM 4K
Block Diagram
Figure 21 EEPROM 4K Block Diagram
Module Memory Map
Overview The memory data is accessible in the address range $x000 - $xFFF and
can be re-mapped to any 4k boundary in the MCU address range. After
reset the MCU register block will be mapped on top of the EEPROM in
the address range $0000 - $03FF. The EEPROM module contains a
bank of control and status registers in the same address space INITRG
+$110 - INITRG +$10B.
EEPROM Block
2k * 16-Bits
Module Bus Interface
Star12 Bus
Control
Registers
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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