Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

EEPROM 4K
MC9S12DP256 — Revision 1.1
EEPROM 4K
Overview
The 4k byte EEPROM module serves as electrically erasable and
programmable, non-volatile data memory without requiring external
programming voltage sources.
The EEPROM may be read as either bytes, aligned words or misaligned
words. Access time is one bus cycle for byte and aligned word and two
bus cycles for misaligned word read. Write operations for program or
erase are only allowed as aligned word accesses. The 4k byte array is
organized in 2048 rows of 2 bytes. An erase sector contains 2 rows. The
erase mode supports erase sector of 4 bytes as well as a mass erase of
the entire 4k byte block.
The programming voltage required to program and erase the EEPROM
is generated internally by on-chip charge pumps. Program and erase
operations are performed by a command driven interface from the
microcontroller using an internal state machine. It is not possible to read
from the EEPROM block while it is being erased or programmed.
The EEPROM has hardware interlocks which protect data from
accidental corruption. The protected area is located at the upper address
end of the EEPROM module ($xxxx – $xFFF). The size of the protected
area can be set from 0 to 512 bytes in multiples of 64 bytes and grows
downwards from address $xFFF.
Features
• 4k bytes of EEPROM
– Single supply program and erase.
– Automated program and erase algorithm.
– Interrupt on command completion.
– Fast sector erase and word program operation.
– Flexible protection scheme against accidental program or
erase.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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