Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Flash EEPROM 256K
MC9S12DP256 — Revision 1.1
Flash EEPROM 256K
Figure 20 256K (4 Blocks) Flash Interrupt Implementation.
CAUTION:
When programming or erasing Flash Block 0 the interrupt vectors are
not readable. It is therefor not recommended to program or erase the
Flash Block 0 with interrupts enabled.
Recovery from
STOP or WAIT
The module can recover the part from WAIT, if the interrupts are
enabled.
There is no capability to recover from STOP.
block0 CBEIF
Block0 select
block1 CBEIF
Block1 select
block0 CCIF
Block0 select
block1 CCIF
Block1 select
CBEIE
CCIE
Flash
Interrupt
Request
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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