Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Flash EEPROM 256K
Interrupt Operation
MC9S12DP256 — Revision 1.1
Flash EEPROM 256K
Wait Mode When the MCU enters WAIT mode and any command is active (CCIF =
0) the command will be completed. If enabled, the CCIF interrupt can be
used to waken the MCU out of Wait mode.
Stop Mode No low power options exist for this module in stop mode. If a command
is active (CCIF = 0) when the MCU enters the STOP mode, the
command will be aborted and the high voltage circuitry to the Flash array
will be switched off.
Interrupt Operation
This module can generate an interrupt when all commands are
completed or the address, data and command buffers are empty.
Interrupt Sources
NOTE:
Vector addresses and their relative interrupt priority are determined at
the MCU level.
The following algorithm is used for generating interrupt via the relevant
block (see Figure 20).
This system uses the CBEIE and CBEIF as well as the block select bits
(BLKSEL) to discriminate for the interrupt generation. By taking account
of the selected block, the system is prevented from generating false
interrupts when the command buffer is empty in an unselected block.
Table 35 Flash 256K Interrupt Sources
Interrupt Source Interrupt Flag Local Enable
Global (CCR)
Mask
Flash Address, Data
and Command Buffers
empty
CBEIF
Flash 0,1,2 or 3
CBEIE I Bit
All Commands are
completed
CCIF
Flash 0,1,2 or 3
CCIE I Bit
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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