Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Flash EEPROM 256K
MC9S12DP256 — Revision 1.1
Flash EEPROM 256K
External Pin Descriptions
This module does not have external pins relevant for the user.
Reset Initialization
Out of reset the module holds core activity while the Protection and
Security registers are loaded from Flash 0. Thereafter, the Flash module
is immediately accessible, operating in read mode.
If a reset occurs while any command is in progress that command will be
immediately aborted. The state of the word being programmed or the
sector / block being erased is not guaranteed.
Modes of Operation
Security Modes The flash module provides the necessary security information to the rest
of the chip. This information is stored within a byte in the flash block 0
($FF0F). This byte is read automatically after each reset and stored in a
volatile register. This information also protects the flash module from
intrusive reads via the external bus interface or the BDM mode. The
customer however can disable the security by providing a 64 bit key.
Low Power Options
When the array or the registers are not being accessed clocking to the
register block is shut off to save power. The only exceptions to this are
the flag bits in the FSTAT registers which are updated by internal state
machines.
Run Mode No special current saving modes available.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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