Datasheet

Flash EEPROM 256K
MC9S12DP256 — Revision 1.1
Flash EEPROM 256K
FPROT Ñ Flash
Protection
Register
Read: Anytime
Write: Only in special modes
This register is banked.
The flash protection registers are loaded during the reset sequence from
address $FF0D for flash block 0, $FF0C for flash block 1, $FF0B for
flash block 2 and $FF0A for flash block 3. This is indicated by the “F” in
the reset row of the register diagram. This register determines whether
a whole block or subsections of a block are protected against accidental
program or erase. Each flash block can have two protected areas, one
starting from relative address $8000 (called lower) towards higher
addresses and the other growing downwards from $FFFF (called
higher). While the later is mainly targeted to hold the boot loader code
since it covers the vector space (flash 0), the other area may be used to
keep critical parameters. Trying to alter any of the protected areas will
result in a protect violation error and bit PVIOL will be set in the Flash
Status Register FSTAT. A mass erase of the full 64K byte block is only
Table 31 Register Bank Selects
BKSEL[1:0] Description
00 Flash 0
01 Flash 1
10 Flash 2
11 Flash 3
Address Offset: $0004
Bit 7 654321Bit 0
Read: FPOPEN F FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0
Write:
Reset: FFFFFFFF
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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